G. Heinz

To accelerate pipelining of digital circuits (microprocessors), it is necessary to balance the delays on all bit-paths. We developed solutions with tree-structures, that could be used for design automation. Tree-like representations allow a balanced delay mapping in standard cell layout and in logic structure.

The slides represent results of the last research project (1990) of my research group at the former (GDR-) Academy of Sciences (Akademie der Wissenschaften, Zentralinstitut für Kybernetik und Informationsprozesse, ZKI-Berlin: Kurstr.33 und Rudower Chaussee 5, Geb. 13.7) in team with

- Friedrich-Karl Staats,
- Dr. Helmut Jahne,
- Dr. Juergen Sieck,
- Torsten Hoffmeister and
- Uwe Schroeder.

The idea covered the acceleration of pipelining for design-automated standard-cell architectures. Comparable simple it was done for a new generation of microprocessors.

Different copies of this lecture went to design centers of eminent companies, like VLSI-Technology, Intel, Mentor and Cadence. However, this idea maight have inspired some VHDL-synthesizer tools.

After 15 years only the overhead slides left, we had no spirit to write a paper in this hard years. After re-unification the Akademy was closed by the new department. In April 1991 I went to Hannover to built up the SICAN design center (now Infineon/Sci-Works). The first ASIC of Sican (1991) was a 330.000 transistor HDTV-image processor we made for Digital Video Systems Hannover.

Please use 'Save as', the files have 1.5 ... 4 MB each (total 46 pages).

Introduction

About Tree Structures

Design Example

How a Generator Works

Applications
 
 
 

Mail to heinz@gfai.de